Dynamic RAMs (hereinafter referred to as DRAMs) have been recently required to be usable in a flexible manner in a variety of modes. There are nibble mode type of DRAMs that are available which are designed to simultaneously read data consisting of a plurality of bits of data to a plurality of pairs of bus lines, and to output the data read out to the respective pairs of bus lines one by one in order to increase a data reading speed. There are proposed a variety of extended nibble modes in the nibble mode type of DRAMs.
A DRAM of the conventional nibble mode type is shown in FIG. 14. A memory cell array 11 includes a plurality of memory cells. To the array 11 are connected a row decoder 12, a sense amplifier and input/output (I/O) gate 13, and a column decoder 14. To the sense amplifier and I/O gate 13 is connected a gate circuit 15, to which is connected a data output buffer 16.
To the row decoder 12 is connected a row address buffer 17, which feeds to a row decoder 12 an external address signal AD including a plurality of bits input from an unillustrated controller unit.
A row controller 18 controls the row decoder 12 and the row address buffer 17 based on the levels of a row address strobe signal RAS and a column address strobe signal CAS, both serving as address activating signals.
To the column decoder 14 is connected a column address buffer 19, which feeds to the column decoder 14 an external address signal AD including a plurality of bits input from the controller.
A column controller 20 controls the sense amplifier and I/O gate 13, the column decoder 14, and the column address buffer 19 based on the level of an output signal of an AND circuit 21 to which a control signal RASZ from the row controller 18 and the column address strobe signal CAS are input.
A clock generating circuit 22 including an odd number of inverter circuits receives the column address strobe signal CAS, and outputs to a nibble counter 23 a clock signal CLK having a negative phase to the signal CAS as shown in FIG. 17. The nibble counter 23 counts the clock signal CLK input from the clock generating circuit 22, and outputs its counted result to a nibble decoder 24. The nibble decoder 24 decodes a counted value of the nibble counter 23, and outputs to a gate control circuit 25 control signals .phi. A to .phi. D shown in FIG. 17.
The gate control circuit 25 takes an AND (logical product) of the control signals .phi. A to .phi. D from the nibble decoder 24 and the clock signal CLK from the clock generating circuit 22, and outputs control signals .phi. 11 to .phi. 14 shown in FIG. 17 to the gate circuit 15 so as to control the gate circuit 15.
A data input buffer 26 is connected to the sense amplifier and I/O gate 13, and receives a write data Din based on a control signal from an unillustrated write clock generator.
FIGS. 15 and 16 show in detail the memory cell array 11, the sense amplifier and I/O gate 13, the gate circuit 15, and the data output buffer 16. As shown in FIG. 15, a data bus 30 includes four pairs of data bus lines DB0, DB0 to DB3, DB3, to which pairs of bit lines BL0, BL0 to BL3, BL3 are connected, respectively. The pairs of bit lines BL0, BL0 to BL3, BL3 are connected to memory cells 32 each having one end thereof connected to a word line WL through gate transistors T1 and a sense amplifier 31.
On the respective pairs of data bus lines DB0, DB0 to DB3, DB3 are arranged amplifiers 33. Gate circuits 15 each including nMOS transistors T2, T3 are provided at the output sides of each amplifier 33 as shown in FIG. 16. The control signal .phi. 11 is input to gates of the nMOS transistors T2, T3 arranged on the pair of bus lines DB0, DB0. The control signal .phi. 12 is input to gates of the nMOS transistors T2, T3 arranged on the pair of bus lines DB1, DB1. The control signal .phi. 13 is input to gates of the nMOS transistors T2, T3 arranged on the pair of bus lines DB2, DB2. The control signal .phi. 14 is input to gates of the nMOS transistors T2, T3 arranged on the pair of bus lines DB3, DB3.
Each of the data bus lines DB0 to DB3 are connected to a common inverter circuit 34 after the transistors T2, while the data bus lines DB0 to DB3 are connected to a common inverter circuit 35 after the transistors T3. The data output buffer 16 includes nMOS transistors T4, T5 connected in series between a power supply VCC and a ground GND. The inverter circuit 34 is connected to a gate terminal of the transistor T4 while the inverter circuit 35 is connected to a gate terminal of the transistor T5. The data output buffer 16 outputs an output signal Dout in the form of a logic value "1" or "0" in accordance with output signals of the inverter circuits 34, 35.
In the DRAM thus constructed, a read cycle is started if the column address strobe signal CAS is in the high level (H-level) when the row address strobe signal RAS is switched to a low level (L-level) as shown in FIG. 17. After either one of the word lines WL is selected in accordance with a row address ADR of the address signal AD, a column address ADC is fed and a column selection signal CL0 turns to H-level. Thereupon, data written in the specified memory cells 32 on the respective pairs of bit lines BL0, BL0 to BL3, BL3 are, via each gate transistor T1 output to the corresponding pairs of data bus lines DB0, DB0 to DB3, DB3, and each data is amplified by the amplifiers 33 respectively.
Then, the control signals .phi. 11 to .phi. 14 are generated by the gate control circuit 23 based on the clock signal CLK from the clock generating circuit 22 and the control signals .phi. A to .phi. D from the nibble decoder 24. Upon receipt of the control signals .phi. 11 to .phi. 14, the transistors T2, T3 arranged on the pairs of data bus lines DB0, DB0 to DB3 are turned on, and thereby the data read out through the data bus lines DB0, BD0 to DB3, DB3 are output through the data output buffer 16 sequentially.
However, in the prior art DRAM, as shown in FIG. 17, the column address ADC of the address signal latched at leading edges of the row address strobe signal RAS and the column address strobe signal CAS is set as an initial address of the nibble counter 23 in the same cycle defined between a fall of the row address strobe signal RAS and a rise thereof. Further, the column selection signal CL0 is maintained in the H-level so as to read out the data to the pairs of data bus lines DB0, DB0 to DB3, DB3. Accordingly, when the addresses corresponding to the number of bits constituting the nibble counter 23 (normally, four bits) are changed from an initial address, the address returns to the initial address, with the result that the output signal Dout outputs again the same data repeatedly.
In order to prevent the same data from being repeatedly output, the read cycle is started by changing the row address strobe signal RAS to the L-level immediately after changing the same to the H-level at the time when the addresses corresponding to the number of bits constituting the nibble counter 23 (normally, four bits) are changed. However, according to this method, it takes time until the first data is output as shown in FIG. 17, thereby suffering the problem of being incapable of increasing a data reading speed.